It is well known to transmit bits of data between integrated circuit components according to a system clock. Typically, one data bit is transmitted on each clock edge, whereby sampling may occur on the rising or falling edge of the clock signal. Continuing improvements in microprocessor design allow for faster clock speeds, which allow for greater data transmission rates. However, there are practical constraints associated with increasing clock speeds. For example, faster clock speeds result in larger power consumption, thermal dissipation problems, and increased electromagnetic interference.
In view of the foregoing, it would be highly desirable to more fully utilize existing clock speeds. That is, it would be highly desirable to transport more information in response to a clock edge. Such a technique would allows improved processing speeds without increasing clock speed.